Programmable Logic Device CPLD FPGA Controller Single-chip Microcomputer GW2A-LV18QN88C8/I7
The GW2A FPGA of Gowin Semiconductor belongs to the Chenxi family 2 series, with abundant internal resources and features
High-performance DSP resources, high-speed LVDS interfaces and abundant BSRAM memory resources, this
Some embedded resources, combined with a streamlined FPGA architecture and 55nm process, make the GW2A FPGA applicable
In high-speed and low-cost application scenarios.
Gao Yun Semiconductor provides a new generation of FPGA hardware development environment independently developed for the market, supporting
With the GW2A series FPGA products, it is capable of completing FPGA synthesis, layout, routing, and data generation
One-stop services including file streaming and downloading.
1.1 Feature Overview
<s:1> Low power consumption - 55nm SRAM process - Nuclear voltage: 1.0V - supports dynamic clock on/off
Supports multiple I/O level standards - LVCMOS33/25/18/15/12;
LVTTL33,SSTL33/25/18 I, II,
"SSTL15; HSTL18 I, II, HSTL15
"I;" PCI, LVDS25, RSDS,
LVDS25E, BLVDSE, MLVDSE,
LVPECLE, RSDSE - provides input signal hysteresis options - provides output signal drive current options - offers an independent Bus for each I/O
Keeper, pull-up/pull-down resistor and Open
Drain output options - Supports hot plugging
<s:1> GPIO supports MIPI D-PHY RX/TX - supports MIPI CSI-2 and MIPI DSI
The interface between RX and TX devices has a single transmission rate
Channel up to 1.2Gbps - Two IO types are available: TLVDS,
DS102-2.7.6
ELVDS
<s:1> High-performance DSP module - high-performance digital signal processing capability - supports 9x 9, 18x 18, 36x 36bit
Multiplication operations and a 54bit accumulator - supports cascading of multiple multipliers - supports register pipeline and bypass functions - pre-addition operations implement filter functions - supports bucket-shift registers
Youdaoplaceholder0 Rich basic logic unit - 4 input LUT(LUT4) - supports shift registers and distributed memory
Supports multiple modes of static random access memory - supports dual-port, single-port and pseudo-dual-port
Mouth pattern
Youdaoplaceholder0 Flexible PLL resources - implementing clock multiplier, division and phase shift - global clock network resources
Self-programming configuration mode - supports JTAG configuration mode - Supports 4 GowinCONFIG configuration modes
Formula: SSPI, MSPI, CPU
SERIAL - Supports direct programming in JTAG and SSPI modes
SPI Flash, other modes can be programmed via IP - supports data stream file encryption and security bit Settings
Packaging and transportation instructions
- According to the standard export packaging.
Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.
Q&A
1. How to obtain the price?
We usually quote within 24 hours after receiving your inquiry (except weekends and holidays). If you are in urgent need of a price, please send us an email or contact us in any other way so that we can provide you with a quotation.
2. What is your delivery time?
This depends on the quantity of the order and the season in which you place the order. Usually, we can ship the goods within 7 to 15 days (for small batches), and for large batches, it takes about 30 days.
3. What are your payment terms?
Factory price, 30% deposit, 70%T/T payment before shipment.
4. What is the mode of transportation?
It can be transported by sea, air or express delivery (EMS, UPS, DHL, TNT, FEDEX, etc.). Please confirm with us before placing an order.
5. How do you help our business establish a long-term and good relationship?
We maintain good quality and competitive prices to ensure that our customers benefit.
2. We respect every customer as our friend. We do business with them sincerely and make friends with them, no matter where they come from.
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15552FF 40Kbits FPGA Field Programmable Gate Array GW2A-LV18QN88C8/I7 Images
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